The present invention relates to lowering the operating voltage of, and lowering the power consumption by, semiconductor memory devices.
FIG. 6 illustrates a known SRAM circuit. The SRAM includes a number of memory cells 1A through 1D disposed in a memory array. Since those memory cells have the same configuration, the memory cell 1A will be described as an example. The memory cell 1A is composed of two load transistors MP1A and MP2A, two transfer transistors MN1A and MN2A, and two drive transistors MN3A and MN4A. The gates of the two transfer transistors MN1A and MN2A are coupled to a word line WLn, while the drains thereof are coupled to bit lines BIT0 and NBIT0. The sources of the two load transistors MP1A and MP2A are coupled to a high voltage power supply VDD. The sources of the two drive transistors MN3A and MN4A are coupled to a low voltage power supply VSS. The load transistors MP1A and MP2A and the drive transistors MN3A and MN4A form two latch circuits. The respective outputs of the latch circuits are connected to the sources of the transfer transistors MN1A and MN2A.
In the SRAM illustrated in FIG. 6, the reference marks 2A and 2B denote precharge-equalize circuits, which are coupled to bit line pairs (BIT0, NBIT0) and (BIT1, NBIT1), respectively, and to which a precharge signal PR is inputted. The reference marks 3A and 3B denote column selectors, which are coupled to the bit line pairs (BIT0, NBIT0) and (BIT1, NBIT1), respectively, and to which column signals CA0 and CA1 are inputted, respectively. The reference numeral 4 indicates a data write circuit, which is connected to the column selectors 3A and 3B via a pair of busses BUS and NBUS.
Hereinafter, a data write operation performed by the SRAM will be described with reference to a timing chart shown in FIG. 7.
When data is written, one of the bit lines BIT0 and NBIT0 selected by a column selector (3A, for example) from among the bit lines BIT0, NBIT0, BIT1, and NBIT1 that have been precharged to the high voltage power supply VDD voltage by the precharge-equalize circuits 2A and 2B, is inverted to the low voltage VSS by the write circuit 4. Next, a selected word line (WLn, for example) is asserted to bring the transfer transistors MN1A and MN2A in the memory cell 1A into conduction, so that the data is written into the memory cell 1A.
To evaluate data write operations, “write margin” is used, for example, in the journal (1992 Vol.J75 C-II No. 7 pp. 350–361) published by the Institute of Electronics, Information and Communication Engineers. The write margin is defined as margin for rewriting data in a memory cell into the reverse data. As in the SRAM illustrated in FIG. 6, since the respective sources of the drive transistors MN3A through MN4D are coupled to the low voltage power supply VSS, the lower the high voltage power supply VDD, the smaller the write margin becomes.
Accordingly, in the SRAM illustrated in FIG. 6, in a case of a low voltage of the high voltage power supply VDD, the write margin becomes small, making it difficult to write the reverse data of the previously written data. Further, in the SRAM illustrated in FIG. 6, one of the bit line pair BIT0 and NBIT0 connected to the memory cell 1A, into which the data is to be written, is fully amplified from the high voltage VDD to the low voltage VSS, causing an increase in current consumption during the write operation.
In order to solve the above problems, as shown in FIG. 8, in the Japanese Laid-Open Publication No. 8-180684, for example, drive transistors (MN3A, MN4A, MN3C and MN4C) through (MN3B, MN4B, MN3D and MN4D) included in memory cells (1A, 1C) through (1B, 1D) located in the respective same rows share respective common source lines. The common source lines are controlled by source potential control signals SLn through SL0 in such a manner that during a write operation, one of the common source lines for the drive transistors is made to float so that data is written into a memory cell with the potential difference between the bit line pair being smaller than the potential difference (VDD−VSS) between the high and low voltages VDD and VSS. In this manner, a decrease in consumption power is achieved.
Nevertheless, in the conventional semiconductor memory device shown in FIG. 8, in a case where the bit line BIT0 and NBIT0 pair, e.g., is selected, if a word line WLn, e.g., is chosen, in the selected memory cell 1A, the transfer transistors MN1A and MN2A are conducting, while the source potential control signal SLn makes the sources of the drive transistors MN3A and MN4A float. Consequently, the potential difference between the bit lines BIT0 and NBIT0 is transmitted to the memory cell 1A, thereby allowing the data to be written. However, also in the unselected memory cell 1C located in the same row, the transfer transistors MN1C and MN2C are brought into conduction, while the sources of the drive transistors MN3C and MN4C float, such that data at storage nodes DC and NDC might be rewritten in the unselected memory cell 1C as well. Therefore, the multiple memory cells 1A and 1B connected to the same word line (WLn, for example) cannot be selected by the column selectors 3A and 3B.